/**
 * NOT STRONG ENOUGH TO HANDLE WHEN (@(posedge write) read==1)
 **/

module mem (
    inout [7 : 0] data,
    input [4 : 0] addr,
    input read, write
);
    reg [7 : 0] memory [0 : 31];
    assign data = read? memory[addr] : data; // 8'bZZZZ_ZZZZ;
    always @(posedge write) begin
        memory[addr] = data;
    end
endmodule
